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test and measurement products 1 www.semtech.com edge6435/6436 per-pin electronics companion dac description features applications revision 3 / august 25, 2006 automated test equipment (ate) cost sensitive applications requiring multiple programmable voltage and currents the edge6435/6436 features 2 ranks of input latches into each dac, whereby all dac values may be updated at one time. for automated test equipment, the edge6435/6436 can support pin electronics and parametric measurement units whose outputs are in the range of ?.25v to +13v, and driver super voltages to +13v after calibration. it provides 10 or 5 per pin levels for 4 or 8 channels respectively. the edge6435/6436 is designed such that dacs may be shared for various levels whereby minimizing the total number of dacs required in a specific application. the edge6435/6436 is a low-cost, 40-channel, monolithic ate level dac solution manufactured in a wide-voltage bi-cmos process. the edge6435/6436 features independent buffered voltage and current outputs that are serially programmed and can be used to provide all of the reference levels required for up to 8 channels of pin electronics in an ate system. designated v oltage output dacs wide voltage range (16.75v) adjustable full-scale range adjustable minimum offset voltage 13-bit resolution 11-bit accuracy (e6436) 10-bit accuracy (e6435) selectable v oltage/current output dacs wide voltage/current range (16.75v/2 ma) adjustable full-scale range adjustable minimum offset configurable as either voltage or current output 13-bit resolution 11-bit accuracy (e6436) 10-bit accuracy (e6435) designated current output dacs 1.6 ma range adjustable full-scale range 6-bit resolution on-chip, digital storage of offset and gain calibration coefficients allow the e6435/6436 output levels to be programmed using ?deal code? helping to reduce some of the complexity and time normally associated with programming level dacs in ate systems. pincast allows the edge6435/6436 to further reduce this complexity and time by allowing channels across multiple edge6435/6436 devices to be digitally assigned to up to 8 distinct sets that can be addressed and programmed with a limited number of instructions. 40 dacs partitioned into 4 groups for 4 or 8 pin channels wide voltage output range ( 16.75v range) 24 voltage dacs per package 8 voltage / current dacs per package 8 current dacs per package adjustable full-scale range and offset per group dut gnd or analog gnd reference per group self-calibrating dacs via internal offset, gain registers two offset, gain registers to support sharing of dacs dac programming per channel or set of channels readback of dac input data and output value small 100-pin mqfp package low-cost, highly integrated multi-dac solution
2 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com functional block diagram update dacen store load rank reset* testmode shiftout* dac 0 dac 39 vouta voutb voutc ioutc ioutd vouta voutb voutc ioutc ioutd vouta voutb voutc ioutc ioutd vouta voutb voutc ioutc ioutd channel 0 channel 1 channel 2 channel 3 sdout dacout ldout sdin clkin 4 2 2 2 2 4 2 2 2 2 4 2 2 2 2 4 2 2 2 2
3 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com pin description e m a n n i p# n i pn o i t p i r c s e d s e i l p p u s r e w o p c c v a6 7 , 8 5 , 9 2) y l p p u s r e f f u b t u p t u o ( s n i p y l p p u s g o l a n a e v i t i s o p e e v a, 8 2 , 7 2 , 2 2 , 3 , 2 7 7 , 3 7 , 1 6 , 7 5 s n i p y l p p u s g o l a n a e v i t a g e n d d v a6 9 , 4 7 , 0 6 , 6 2 , 1 2) y l p p u s c a d e r o c ( s n i p y l p p u s g o l a n a e v i t i s o p d n g a9 9 , 5 7 , 9 5 , 5 2 , 0 2s n i p d n u o r g y l p p u s g o l a n a d d v d7 6 , 5 6s n i p t u p n i y l p p u s l a t i g i d d n g d8 6 , 4 6s n i p d n u o r g y l p p u s l a t i g i d f e r v9 6 , 3 6 , 4t u p n i e g a t l o v e c n e r e f e r s n i p o / i l a t i g i d n i k l c4 1. n i p t u p n i k c o l c n i d s2 1 t f i h s t u p n i 5 3 4 6 e e h t o t n i s d r o w t i b - 4 2 d a e r o t d e s u s i t a h t n i p t u p n i a t a d l a i r e s . r e t s i g e r d a o l5 1 t f i h s t u p n i a t a d l a i r e s e h t m o r f a t a d f o r e f s n a r t e h t s r e g g i r t t a h t n i p t u p n i l a t i g i d . z h m 3 3 o t p u t a r e t s i g e r c a d l a r t n e c e h t o t r e t s i g e r e r o t s0 1. s e h c t a l a k n a r e h t e t a d p u o t d e s u s i t a h t n i p t u p n i l a t i g i d e t a d p u9 . s e h c t a l b k n a r e h t e t a d p u o t d e s u s i t a h t n i p t u p n i l a t i g i d k n a r6 6 c a d e h t s a s e h c t a l b k n a r r o a k n a r e h t n i a t a d r e h t i e s t c e l e s t a h t n i p t u p n i l a t i g i d . t u p n i t a m r o f1 1 g n i d o c e d " l e n n a h c - 8 " r o " l e n n a h c - 4 " n e e w t e b t c e l e s o t d e s u n i p t u p n i l a t i g i d . s e m e h c s * t e s e r7 . e t a t s n w o n k a o t n i t i g n i c a l p y b 5 3 4 6 e e h t e z i l a i t i n i o t d e s u s i t a h t n i p t u p n i l a t i g i d n e c a d6 r o ) s c a d t u p t u o e g a t l o v ( v 0 ~ s t u p t u o c a d l l a t e s o t d e s u s i t a h t n i p t u p n i l a t i g i d . ) s c a d t u p t u o t n e r r u c ( a m 0 ~ t u o d s7 1. n i p t u p t u o a t a d l a i r e s s n i p c i t s o n g a i d e d o m _ t s e t6 1 . s n o i t c n u f t u o _ d l d n a t u o _ c a d e h t e l b a s i d / e l b a n e o t d e s u s i t a h t n i p t u p n i l a t i g i d t u o _ c a d4 5 d e t c e l e s a f o l e v e l t u p t u o e h t s y a l p s i d t a h t n i p t u p t u o e g a t l o v g o l a n a e c n a d e p m i h g i h . n i p e d o m _ t s e t e h t g n i s u d e l b a n e n e h w ) s c i t s o n g a i d l e v e l m e t s y s r o f d e s u ( c a d * t u o t f i h s8 e h t h g u o r h t a t a d l a i r e s f o n o i s s i m s n a r t e h t n i g e b o t d e s u s i t a h t n i p t u p n i l a t i g i d . n i p t u o _ d l t u o _ d l3 1 r o a k n a r d e t c e l e s a n i d e r o t s e u l a v y r a n i b e h t y a l p s i d o t d e s u n i p t u p t u o a t a d l a i r e s . h c t a l b k n a r
4 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com pin description (continued) e m a n n i p# n i pn o i t p i r c s e d s c a d t u p t u o e g a t l o v t i b - 3 1 0 _ a t u o v 1 _ a t u o v 2 _ a t u o v 3 _ a t u o v 4 _ a t u o v 5 _ a t u o v 6 _ a t u o v 7 _ a t u o v 8 _ a t u o v 9 _ a t u o v 0 1 _ a t u o v 1 1 _ a t u o v 2 1 _ a t u o v 3 1 _ a t u o v 4 1 _ a t u o v 5 1 _ a t u o v 3 9 2 9 1 9 0 9 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 8 9 7 8 7 . s n i p t u p t u o c a d e g a t l o v a p u o r g 0 _ b t u o v 1 _ b t u o v 2 _ b t u o v 3 _ b t u o v 4 _ b t u o v 5 _ b t u o v 6 _ b t u o v 7 _ b t u o v 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 . s n i p t u p t u o c a d e g a t l o v b p u o r g s c a d t u p t u o t n e r r u c / e g a t l o v e l b a t c e l e s t i b _ 3 1 0 _ c t u o v 1 _ c t u o v 2 _ c t u o v 3 _ c t u o v 4 _ c t u o v 5 _ c t u o v 6 _ c t u o v 7 _ c t u o v 8 3 1 4 2 4 5 4 6 4 9 4 0 5 3 5 . s n i p t u p t u o c a d e g a t l o v c p u o r g 0 _ c t u o i 1 _ c t u o i 2 _ c t u o i 3 _ c t u o i 4 _ c t u o i 5 _ c t u o i 6 _ c t u o i 7 _ c t u o i 9 3 0 4 3 4 4 4 7 4 8 4 1 5 2 5 . s n i p t u p t u o c a d t n e r r u c c p u o r g s c a d t u p t u o t n e r r u c t i b - 6 0 _ d t u o i 1 _ d t u o i 2 _ d t u o i 3 _ d t u o i 4 _ d t u o i 5 _ d t u o i 6 _ d t u o i 7 _ d t u o i 8 1 9 1 1 0 0 1 8 9 7 9 5 9 4 9 . s n i p t u p t u o c a d t n e r r u c d p u o r g
5 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com pin description (continued) e m a n n i p# n i pn o i t p i r c s e d s n o i t c e n n o c r o t s i s e r r e t s a m _ r0 7 d n a , b _ n i a g v _ r , a _ n i a g v _ r h t i w n o i t a n i b m o c n i d e s u n o i t c e n n o c r o t s i s e r l a n r e t x e e g a t l o v c d n a , b , a p u o r g e h t r o f e g n a r t u p t u o m u m i x a m e h t t e s o t c _ n i a g v _ r . s c a d t u p t u o a _ n i a g v _ r1 7 e h t t e s o t r e t s a m _ r h t i w n o i t a n i b m o c n i d e s u n o i t c e n n o c r o t s i s e r l a n r e t x e . s t u p t u o c a d e g a t l o v a p u o r g e h t r o f e g n a r m u m i x a m b _ n i a g v _ r4 2 e h t t e s o t r e t s a m _ r h t i w n o i t a n i b m o c n i d e s u n o i t c e n n o c r o t s i s e r l a n r e t x e . s t u p t u o c a d e g a t l o v b p u o r g e h t r o f e g n a r m u m i x a m c _ n i a g v _ r6 5 e h t t e s o t r e t s a m _ r h t i w n o i t a n i b m o c n i d e s u n o i t c e n n o c r o t s i s e r l a n r e t x e . s t u p t u o c a d e g a t l o v c p u o r g e h t r o f e g n a r m u m i x a m a _ t e s f f o _ r2 7 e g a t l o v a p u o r g r o f e g a t l o v t e s f f o e s a b e h t t e s o t d e s u n o i t c e n n o c r o t s i s e r l a n r e t x e . s t u p t u o c a d b _ t e s f f o _ r3 2 e g a t l o v b p u o r g r o f e g a t l o v t e s f f o e s a b e h t t e s o t d e s u n o i t c e n n o c r o t s i s e r l a n r e t x e . s t u p t u o c a d c _ t e s f f o _ r5 5 e g a t l o v c p u o r g r o f e g a t l o v t e s f f o e s a b e h t t e s o t d e s u n o i t c e n n o c r o t s i s e r l a n r e t x e . s t u p t u o c a d c _ n i a g i _ r2 6 t n e r r u c c p u o r g e h t r o f e g n a r m u m i x a m e h t t e s o t d e s u n o i t c e n n o c r o t s i s e r l a n r e t x e . s t u p t u o c a d d _ n i a g i _ r5 t n e r r u c d p u o r g e h t r o f e g n a r m u m i x a m e h t t e s o t d e s u n o i t c e n n o c r o t s i s e r l a n r e t x e . s t u p t u o c a d
6 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com pin description (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ioutd_2 avee avee vref r_igain_d dacen reset* shiftout* update store format sdin ld_out clkin load test_mode sdout ioutd_0 ioutd_1 agnd avdd avee r_offset_b r_vgain_b agnd avdd avee avee avcc voutb_0 voutb_1 voutb_2 voutb_3 voutb_4 voutb_5 voutb_6 voutb_7 voutc_0 ioutc_0 ioutc_1 voutc_1 voutc_2 ioutc_2 ioutc_3 voutc_3 voutc_4 ioutc_4 ioutc_5 voutc_5 voutc_6 ioutd_3 agnd ioutd_4 ioutd_5 avdd ioutd_6 ioutd_7 vouta_0 vouta_1 vouta_2 vouta_3 vouta_4 vouta_5 vouta_6 vouta_7 vouta_8 vouta_9 vouta_10 vouta_11 vouta_12 vouta_13 vouta_14 vouta_15 avee avcc agnd avdd avee r_offset_a r_vgain_a r_master vref dgnd dvdd rank dvdd dgnd vref r_igain_c avee avdd agnd avcc avee r_vgain_c r_offset_c dac_out voutc_7 ioutc_7 ioutc_6 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 edge6435ahf 100 lead - 14 x 20 mqfp with internal heat spreader (top view)
7 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com circuit description chip overview the edge6435/6436 provides 40 output levels. these outputs can easily be configured to generate the specific analog voltage and current requirements for 4 or 8 channels of ate pin electronics including: 3 level driver window comparator active load per pin pmu or ptu without requiring any scaling or shifting via external components. selection of 4 or 8 channel format is via the format input. programming of the chip is done using a 6 wire digital interface comprised of: serial data in clock in load grouping of dacs dacs are separated into 4 or 8 channels of 4 distinct functional groups. groups are defined by: type (voltage or current output) resolution (# of bits) output range output compliance. table 1 defines the dacs on a per group and channel basis. group c dacs have both voltage and current output pins. group c dacs can be individually configured via the serial interface to be either a voltage or current dac (but not both at the same time). tables 3 and 4 identify the code needed to configure group c dacs. please note that 24 clock cycles are required to load the configuration code for each channel. table 1. dac grouping note 1: the max dac range is achieved through specific avcc, avee, and gain resistor settings. see the equations in the "dac voltage output overview", "dac current output overview", and specifications for details. note 2: group c has both voltage and current outputs. e t u b i r t t a p u o r g a p u o r g b p u o r g c p u o r g d p u o r g n i s c a d f o # l a t o t t a m r o f h c 4l e n n a h c r e p 4l e n n a h c r e p 2l e n n a h c r e p 2l e n n a h c r e p 2 t a m r o f h c 8l e n n a h c r e p 2l e n n a h c r e p 1l e n n a h c r e p 1l e n n a h c r e p 1 e p y tvvi / vi n o i t u l o s e r ) s t i b f o # ( 3 13 13 16 : e g n a r t u p t u o ) 1 e t o n ( e g n a r c a d x a m e g n a r t e s f f o v 5 7 . 6 1 v 5 7 . 0 o t v 5 . 3 v 5 7 . 6 1 v 5 7 . 0 o t v 5 . 3 v 5 7 . 6 1 v 5 7 . 0 o t v 5 . 3 r o a m 5 0 . 2 ) 2 e t o n ( a m 6 . 1 t e s f f o t u p t u o e l b a t s u j d as e ys e y t u o v r o f s e y t u o i r o f o n o n e c n a i l p m o ca 0 0 2 a 0 0 2 ) v ( a 0 0 2 ) i ( v 3 + o t 2 . 0 v 3 + o t 2 . 0
8 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com minimum / maximum output voltages see table 2 for the minimum and maximum possible voltages of a voltage output, where: v offset[a:c] is defined in equation 2, and equation 3. resolution the resolution of the dacs in groups a, b and c is: v range_[a:c] / (2 13 1) where v range_[a:c] is defined in equation 4. range the range of the dacs in groups a, b and c is: equation 4. external resistors typically computed for r_master = 100k ? . t able 2. minimum/maximum output voltages circuit description (continued) g n i t t e s c a d b s l . . . b s m v ] c : a [ _ t u o ) v ( h 0 0 0 0 v : a [ _ t e s f f oc] h f f f 1 v ] c : a [ _ x a m voltage outputs dacs (groups a, b, c) the output voltage of each e6435/6436 v out dac is a function of external resistor values (r_master, r_vgain and r_offset), a reference voltage level (v ref ), contents of digital offset and gain registers, and the programmed input code (data). the general equation that describes the output voltage as a function of these variables is presented below as equation 1: equation 1. where: v out [a:c] is the output voltage of a group a, b, or c voltage dac. v ref is an externally applied 2.5v reference voltage r_vgain[a:c] is the value of an external resistor used to set the range for group a, b, or c dacs r_master is the value of an external resistor that sets the bias point/range for the voltage dacs code is the base-10 value of the binary code (data) loaded into the dac shift register (see figures 4 and 5) after it has been modified by the contents of the digitally programmable offset and gain calibration registers as shown in figure 2. v offset[a:c] is the raw dac offset voltage that is programmed using an external resistor per group, r_offset[a:c] as follows: equation 2. as can be seen from equation 1, the accuracy of the dac output voltage after calibration is dependent upon the temperature coefficients of v ref and the external resistors. v out_[a:c] = * 8 * v ref + v offset_[a:c] r_vgain_[a:c] r_master * code 8192 v offset_[a:c] = v ref r_offset_[a:c] r_master v max_[a:c] = + v offset_[a:c] r_vgain_[a:c] r_master 8 * v ref 8191 8192 * * = v range_[a:c] r_vgain_[a:c] r_master 8 * v ref * 8191 8192 *
9 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com circuit description (continued) current output dacs (groups c, d) group c dacs the output current of each group c current dac is a function of an external resistor value (r_igain_c), a reference voltage level (v ref ), contents of digital offset and gain registers, and the input code (data). the general equation that describes the output current as a function of these variables is presented below as equation 5: equation 5. where: i out_c is the output current of the group c current dac v ref is an externally applied 2.5v reference voltage r_igain_c is the value of an external resistor that sets the output current range for group c dacs (60.97k ? r_igain_c 250k ? ) code is the base-10 value of the binary code (data) loaded into the dac shift register (see figures 4 and 5) after it has been modified by the contents of the digitally programmable offset and gain calibraiotn registers as shown in figure 2. group d dacs the output current of each group d dac is a function of an external resistor value (r_igain_d), a reference voltage level (v ref ) and the input code (data). the general equation that describes the output current as a function of these variables is presented below as equation 6: equation 6. where: i out_d is the output current of the group d dac v ref is an externally applied 2.5v reference voltage i out_c = code * 8192 50 x v ref r_igain_c i out_d = data * 64 50 x v ref r_igain_d r_igain_d is the value of an external resistor that sets the output current range for group d dacs (78.12k ? r_igain_d 156.25k ? ) data is the base-10 value of the binary code loaded into the dac shift register (see figures 4 and 5). functional description figure 1 provides a functional block diagram. figures 2 and 3 show details of the data latches and logic for the dacs. the edge6435/6436 features a serial data input to program a channel or set of channel s dacs and functions. the edge6435/6436 also features self- calibrating dac outputs via internal offset and gain registers (figure 2). figures 4 and 5 show the format of the serial input data for 4 pin channel and 8 pin channel formats. figure 6 shows the serial data programming sequence tables 3 and 4 provide the address maps for 4 pin channel and 8 pin channel formats. format format low selects the 4 pin channel format. format high selects the 8 pin channel format.
10 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com circuit description (continued) circuit description (continued) reset* reset* low resets the input shift register (no clkin required), the central register, and input registers. with reset* high, the following leading edge of clkin will cause reset condition to be removed (see figure 21). two clock cycles are required after reset* is set to logic high for the dac outputs to be enabled. programming sequence the dacs are programmed serially (see figures 1 and 6). on each rising edge of clkin, sdin is loaded into a shift register. it requires 24 clocks to fully load the shift register. load following the serial input of a new dac value, then load high for the leading edge of clkin loads the new dac value and its address into the central register. following the loading of the central register, load needs to go low followed by a leading edge of clkin so as to enable the address decoder (see figure 6). store following the load of the central register and the enabling of the address docoder, the channel or set of channels addressed dacs input register or channel function is stored by a clkin with store high. only upon the store of a dac or set of dac s value latch (figure 2) does the edge6435/6436 compute the input to dac s latch a (of rank a). there needs to be at least one clock edge after load is set to logic low before store is set to logic high (see figure 21). update following the store of multiple dac values into rank a dac latches, rank b latches may be updated in parallel with the values of their rank a dac latches by a clkin with update high. there must be at least 16 clock cycles between when store is set to logic low and update is latched to logic high in order to latch the latest data (see figure 21). rank selection referring to figures 1, 2 and 3: rank low selects rank a latches to the dacs (no clkin required). rank high selects rank b latches to the dacs (no clkin required). dacen dacen low forces all dac voltage outputs to ~0v and all current outputs to ~0 ma (no clkin required). with dacen high, then a following leading edge of clkin will cause dacs to be enabled (see figure 23). test mode/shiftout* test_mode is used to enable the ldout and dacout channels. once enabled (testmode = 1), shiftout* can be used to begin transmission of serial data through the ldout pin, or dac outputs can be monitored at the dacout pin (see figure 24) (test_mode functionality does not depend on clkin)). when addressing dac channels that have been assigned to a pincast set , test-mode is internally disabled in order to prevent multiple dac outputs from being connected in parallel and possibly damaging the e6435/ 6436.
11 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com circuit description (continued) belong to none, one, or any combination of up to 8 distinct sets. the address maps show that a channel s dac (or function) may be addressed individually, or a dac (or function) of multiple channels belonging to the same set may be programmed in parallel. figure 11 shows an example of addressing channels by sets. referring to table 3, a channel s function is programmed as indicated in figure 9 (offset and gain selection as well as group c dac v/i output selection, see below). channel s functions (for 13 bit dacs only), with r2 = r1 = r0 = 0, then: d0 = 0: selects 1st offset/gain registers d0 = 1: selects 2nd offset/gain registers d1 = 0: selects voltage output on group c dacs d1 = 1: selects current output on group c dacs referring to table 4 for 8 channel format, and figures 2, 3, 5, 8 and 10, a channel s dacs, set registers and function, etc. are programmed and operate similar to the 4 channel format described above. note: the store of a dac s offset or gain does not result in a dac output change. only upon the store of a dac or set of dac s value does the edge6435/6436 compute the input to dac s a latches. in a tester having multiple edge6435/6436s, dacs or channel functions may be programmed individually or as a set (1 of 8) of channels across all channels. if multiple e6435/6436s are programmed in parallel, individual dac or function programming requires the store input to the associated edge6435/6436 to be applied where all store inputs to other edge6435/6436s are to be inhibited (externally). programming a dac or function of a set of channels requires store input to be applied to all edge6435/6436s. edge6435/6436 s dacs may be updated in parallel following the programming of dacs as individual dacs or sets of dacs. serial programming the edge6435/6436 is programmed with 24-bit serial data (figure 6) in either a 4 channel (figure 4) or 8 channel (figure 5) format. following the input of serial data, it is loaded into a central register by load (figure 1). the central register s contents are stored in the addressed latch by the store input. tables 3 and 4 show the address maps for the 4 and 8 channel formats. referring to table 3 for 4 channel format, a channel s dacs set register or function may be addressed and the stored value changed. for each dac, there are associated multiple latches (figures 2 and 3). for the 13-bit dacs (figure 2) the dac s output is a function of the contents of its value, gain and offset latches. the edge6435/6436 features two gain and offset latches per dac whereby a dac s output may be shared. for example, in ate a dac s value may be shared between a pin driver s high level and a pin s parametric unit s high limit level, where each application requires different offset and gain factors to calibrate each path correctly. gains and offsets are computed externally to the edge6435/6436 in the process of pin channel level calibration in the ate. gains and offsets are stored in the edge6435/6436 in the same manner as other latches. selection of what is stored is determined by the register selection bits in the 24-bit input data (figures 2 and 4). upon storing a 13-bit dac s value, the resultant dac s ((v alue x gain) + offset + 4096 value) is updated by updatea (figure 2) into the dac s output latch of ranka. the contents of all ranka latches may be transferred to rankb latches, in parallel, across multiple edge6435/6436 s by the update input into the edge6435/6436. the rank input into the edge6435/ 6436 selects either ranka or rankb latches for all dacs. for the 6-bit dacs (figure 3) the dac s output is selected from four value latches . referring to table 3, a channels set register may also be programmed. this is an independent 8-bit register per channel which determines the sets to which the channel belongs. figure 7 shows details of programming a channel s set register, which is stored in the edge6435/6436 by the store input. a channel may
12 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com circuit description (continued) figure 1. dac functional block diagram d12-d0 sr4-sr0 a3-a0 c1-c0 m1-m0 r2-r0 13 11 decode and individual dac update programming logic note: not shown is the function of the latched data readback (via ldout) and the dac value readback (via dacout). details of the 'store' latches are shown on the following pages. address and set decoders disable store dacen dacsel0 dacsel1 sdout central register (24 bits) reset reset lclk load clkin sdin reset* format vouta_0 ldout dacout ioutd_3 vouta_1 24-bit shift register r r cr r c r update updatea updatea updatea updateb rank c c r s s d d d7-d0 d d d dac0 dac1 a b dac39 d d a b a b rr d d note: vout, iout names shown for 4 channel format.
13 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com circuit description (continued) n o i t c n u f n o i t c e l e s r e t s i g e r 2 r1 r0 rt c e l e s a t a d c a d0000 r s a r e t s i g e r n i a g0011 r s b r e t s i g e r n i a g0102 r s a r e t s i g e r t e s f f o0113 r s b r e t s i g e r t e s f f o1004 r s figure 2. details of dac data latches for 13 bit dacs (groups a, b, and c) d v v v a b sel d d d d 10 10 13 13 13 13 10 10 10 10 sr0 sr1 sr2 sr3 sr4 r rr + + d d a b calsel dacsel d[12:0] store updatea update rank g g o o a b sel updatea sequence generator d[9:0] d[9:0] d[9:0] d[9:0] 13 4096 key: v: value latch that contains data programmed to a dac (see figures 4 & 5). o: offset latches that are used to store offset calibration coefficients (two offset latches per dac allow the dac to be shared in a system). g: gain latches that are used to store gain calibration coefficients (two gain latches per dac allow the dac to be shared in a system). note: calsel common to all dacs assigned to a channel dac output (code): code = + o v * (g + 4096) 4096
14 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com circuit description (continued) ) s v ( n o i t c e l e s e u l a v 8 d7 dt c e l e s 00a 01b 10c 11d figure 3. details of dac data latches for 6 bit dacs (group d) d va v v d d d d 6 6 sr0 sr1 sr2 sr3 sr4 r dacsel d[12:7] d[8:7] store vb vc vd vs key: va, vb, vc, vd: vs: value latches a, b, c, d value selection latch r d a b updateb rank 6 6 6 2 a b c d m u x
15 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com circuit description (continued) r2 r1 r0 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data c1 c0 a3 a2 a1 a0 address lsb register m0 mode channel lsb msb msb m1 r2 r1 r0 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data c1 c0 a3 a2 a1 a0 address lsb lsb register m0 mode channel lsb msb msb m1 a0 a1 m0 m1 d0 d1 r1 r2 lsb addr. msb addr. lsb data msb data sdin clkin a1 load next set of data a0 ck1 sdout ck24 a0 a1 previous data corresponds to a0 loaded at ck1 t ck figure 4. format of address and data in shift register (4 channel format) figure 5. format of address and data in shift register (8 channel format) figure 6. serial data programming sequence
16 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com figure 7. format of address and data for programming to set register (4 channel format) circuit description (continued) x x x xx x x x d7 d6 d5 d4 d3 d2 d1 d0 data c1 c0 1 1 0 0 address lsb register 0 mode channel lsb msb msb 0 figure 8. format of address and data for programming to set register (8 channel format) x x x xx x x x d7 d6 d5 d4 d3 d2 d1 d0 data c1 c0 1 1 0 a0 address lsb lsb register 0 mode channel lsb msb msb msb 0 figure 9. format of address and data for programming a channel? function (4 channel format) figure 10. format of address and data for programming a channel? function (8 channel format) 0 0 0 xx x x x x x x x x x d1 d0 data c1 c0 1 1 1 0 address lsb register 0 mode channel lsb msb msb 0 0 0 0 xx x x x x x x x x x d1 d0 data c1 c0 1 1 1 address lsb lsb register 0 mode channel lsb msb msb msb 0 a0
17 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com circuit description (continued) x x x xx x x x d1 d2 d3 d4 d5 d6 d7 d0 data c1 c0 1 1 0 0 address lsb register 0 mode store channel msb msb 0 r2 r1 r0 d12 d10 d9 d8 d11 d1 d2 d3 d4 d5 d6 d7 d0 data c1 c0 a3 a2 a1 a0 address lsb lsb lsb channel's set register (channel belongs to sets 4 and 6) 1 channel set selection 1 of 8 selection msb msb msb m1 0 0 0 1 0 1 0 0 compare if set 4 is selected, then channel s dac value or function will be stored . if set 3 is selected, then the channel will not be addressed . figure 11. example of channel? set selection (4 channel format)
18 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com circuit description (continued) table 3. address map (4 channel format) (continued next page) channel functions channel 0 channel 1 channel 2 channel 3 note 1: all 6-bit dacs are programmed with the msb at the d12 bit position and extending down to d7 for the lsb. d[6:0] bit positions are don t cares . 2322212019-16 15-1211109876 543210 0x01 0000 0x1000 8421 8 - 1 8 - 1 8 4 2184 218421 register r2 r1 r0 d12 d11 - d8 d7 - d4 d3 d2 d1 d0 m1 m0 c1 c0 a 3 a 2 a 1 a 0 vouta_0 x x x x x x x x x x 0 0 0 0 0 0 0 0 vouta_1 x x x x x x x x x x 0 0 0 0 0 0 0 1 vouta_2 x x x x x x x x x x 0 0 0 0 0 0 1 0 vouta_3 x x x x x x x x x x 0 0 0 0 0 0 1 1 reserved n / a x x x x x x x x x x 0 0 0 0 n / a voutb_0 x x x x x x x x x x 0 0 0 0 0 1 1 0 voutb_1 x x x x x x x x x x 0 0 0 0 0 1 1 1 voutc_0, ioutc_0 x x x x x x x x x x 0 0 0 0 1 0 0 0 voutc_1, ioutc_1 x x x x x x x x x x 0 0 0 0 1 0 0 1 ioutd_0 x x x x x x x x x x 0 0 0 0 1 0 1 0 ioutd_1 x x x x x x x x x x 0 0 0 0 1 0 1 1 pincast register 0 n / a x x x x x x x x x x 0 0 0 0 1 1 0 0 n / a reserved n / a x x x x x x x x x x 0 0 0 0 1 1 0 1 n / a select rank 1 calibration registers 0 0 0 x x x x x x 0 0 0 0 0 1 1 1 0 select rank 2 calibration registers 0 0 0 x x x x x x 1 0 0 0 0 1 1 1 0 configure group c dacs as vout 0 0 0 x x x x x 0 x 0 0 0 0 1 1 1 0 configure group c dacs as iout 0 0 0 x x x x x 1 x 0 0 0 0 1 1 1 0 reserved n / a x x x x x x x x x x 0 0 0 0 1 1 1 1 n / a vouta_4 x x x x x x x x x x 0 0 0 1 0 0 0 0 vouta_5 x x x x x x x x x x 0 0 0 1 0 0 0 1 vouta_6 x x x x x x x x x x 0 0 0 1 0 0 1 0 vouta_7 x x x x x x x x x x 0 0 0 1 0 0 1 1 reserved n / a x x x x x x x x x x 0 0 0 1 n / a voutb_2 x x x x x x x x x x 0 0 0 1 0 1 1 0 voutb_3 x x x x x x x x x x 0 0 0 1 0 1 1 1 voutc_2, ioutc_2 x x x x x x x x x x 0 0 0 1 1 0 0 0 voutc_3, ioutc_3 x x x x x x x x x x 0 0 0 1 1 0 0 1 ioutd_2 x x x x x x x x x x 0 0 0 1 1 0 1 0 ioutd_3 x x x x x x x x x x 0 0 0 1 1 0 1 1 pincast register 1 n / a x x x x x x x x x x 0 0 0 1 1 1 0 0 n / a reserved n / a x x x x x x x x x x 0 0 0 1 1 1 0 1 n / a select rank 1 calibration registers 0 0 0 x x x x x x 0 0 0 0 1 1 1 1 0 select rank 2 calibration registers 0 0 0 x x x x x x 1 0 0 0 1 1 1 1 0 configure group c dacs as vout 0 0 0 x x x x x 0 x 0 0 0 1 1 1 1 0 configure group c dacs as iout 0 0 0 x x x x x 1 x 0 0 0 1 1 1 1 0 reserved n / a x x x x x x x x x x 0 0 0 1 1 1 1 1 n / a vouta_8 x x x x x x x x x x 0 0 1 0 0 0 0 0 vouta_9 x x x x x x x x x x 0 0 1 0 0 0 0 1 vouta_10 x x x x x x x x x x 0 0 1 0 0 0 1 0 vouta_11 x x x x x x x x x x 0 0 1 0 0 0 1 1 reserved n / a x x x x x x x x x x 0 0 1 0 n / a voutb_4 x x x x x x x x x x 0 0 1 0 0 1 1 0 voutb_5 x x x x x x x x x x 0 0 1 0 0 1 1 1 voutc_4, ioutc_4 x x x x x x x x x x 0 0 1 0 1 0 0 0 voutc_5, ioutc_5 x x x x x x x x x x 0 0 1 0 1 0 0 1 ioutd_4 x x x x x x x x x x 0 0 1 0 1 0 1 0 ioutd_5 x x x x x x x x x x 0 0 1 0 1 0 1 1 pincast register 2 n / a x x x x x x x x x x 0 0 1 0 1 1 0 0 n / a reserved n / a x x x x x x x x x x 0 0 1 0 1 1 0 1 n / a select rank 1 calibration registers 0 0 0 x x x x x x 0 0 0 1 0 1 1 0 1 select rank 2 calibration registers 0 0 0 x x x x x x 1 0 0 1 0 1 1 0 1 configure group c dacs as vout 0 0 0 x x x x x 0 x 0 0 1 0 1 1 0 1 configure group c dacs as iout 0 0 0 x x x x x 1 x 0 0 1 0 1 1 1 0 reserved n / a x x x x x x x x x x 0 0 1 0 1 1 1 1 n / a vouta_12 x x x x x x x x x x 0 0 1 1 0 0 0 0 vouta_13 x x x x x x x x x x 0 0 1 1 0 0 0 1 vouta_14 x x x x x x x x x x 0 0 1 1 0 0 1 0 vouta_15 x x x x x x x x x x 0 0 1 1 0 0 1 1 reserved n / a x x x x x x x x x x 0 0 1 1 n / a voutb_6 x x x x x x x x x x 0 0 1 1 0 1 1 0 voutb_7 x x x x x x x x x x 0 0 1 1 0 1 1 1 voutc_6, ioutc_6 x x x x x x x x x x 0 0 1 1 1 0 0 0 voutc_7, ioutc_7 x x x x x x x x x x 0 0 1 1 1 0 0 1 ioutd_6 x x x x x x x x x x 0 0 1 1 1 0 1 0 ioutd_7 x x x x x x x x x x 0 0 1 1 1 0 1 1 pincast register 3 n / a x x x x x x x x x x 0 0 1 1 1 1 0 0 n / a reserved n / a x x x x x x x x x x 0 0 1 1 1 1 0 1 n / a select rank 1 calibration registers 0 0 0 x x x x x x 0 0 0 1 1 1 1 0 1 select rank 2 calibration registers 0 0 0 x x x x x x 1 0 0 1 1 1 1 0 1 configure group c dacs as vout 0 0 0 x x x x x 0 x 0 0 1 1 1 1 0 1 configure group c dacs as iout 0 0 0 x x x x x 1 x 0 0 1 1 1 1 1 0 reserved n / a x x x x x x x x x x 0 0 1 1 1 1 1 1 n / a group d 6-bit i (note 1) n/a group c 13-bit v/i group d 6-bit i (note 1) group b 13-bit v group d 6-bit i (note 1) n/a group b 13-bit v group d 6-bit i (note 1) n/a group b 13-bit v group a 13-bit v group c 13-bit v/i group a 13-bit v group c 13-bit v/i group a 13-bit v dac output pin name data format = 0 bit # hex multiplier 0x10 0000 0x0100 binar y position item
19 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com table 3. address map (4 channel format) ?cont? circuit description (continued) pincast set functions group a dacs group b dacs group c dacs group d dacs 23 22 21 20 19-16 15-12 11 10 9 8 7 6 5 4 3 2 1 0 0x01 0000 0x1000 8 4 2 1 8 - 1 8 - 1 8 4 2 1 8 4 2 1 8 4 2 1 register r2 r1 r0 d1 2 d11 - d8 d7 - d4 d3 d2 d1 d0 m1 m0 c1 c0 a 3 a 2 a 1 a 0 all dacs parallel load of all dacs all dac output pins xxxx x x xxxx100 0 000 0 parallel load of denoted vouta dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). vouta_0 vouta_4 vouta_8 vouta_12 x x x x x x x x x x ps0 1 ps2 ps1 0 0 0 0 parallel load of denoted vouta dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). vouta_1 vouta_5 vouta_9 vouta_13 x x x x x x x x x x ps0 1 ps2 ps1 0 0 0 1 parallel load of denoted vouta dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). vouta_2 vouta_6 vouta_10 vouta_14 x x x x x x x x x x ps0 1 ps2 ps1 0 0 1 0 parallel load of denoted vouta dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). vouta_3 vouta_7 vouta_11 vouta_15 x x x x x x x x x x ps0 1 ps2 ps1 0 0 1 1 reserved n / a x x x x x x x x x x x x x x parallel load of denoted voutb dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). voutb_0 voutb_2 voutb_4 voutb_6 x x x x x x x x x x ps0 1 ps2 ps1 0 1 1 0 parallel load of denoted voutb dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). voutb_1 voutb_3 voutb_5 voutb_7 x x x x x x x x x x ps0 1 ps2 ps1 0 1 1 1 parallel load of denoted voutc or ioutc dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). voutc_0 voutc_2 voutc_4 voutc_6 or ioutc_0 ioutc_2 ioutc_4 ioutc_6 x x x x x x x x x x ps0 1 ps2 ps1 1 0 0 0 parallel load of denoted voutc or ioutc dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). voutc_1 voutc_3 voutc_5 voutc_7 or ioutc_1 ioutc_3 ioutc_5 ioutc_7 x x x x x x x x x x ps0 1 ps2 ps1 1 0 0 1 parallel load of denoted ioutd dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). ioutd_0 ioutd_2 ioutd_4 ioutd_6 x x x x x x x x x x ps0 1 ps2 ps1 1 0 1 0 parallel load of denoted ioutd dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). ioutd_1 ioutd_3 ioutd_5 ioutd_7 x x x x x x x x x x ps0 1 ps2 ps1 1 0 1 1 reserved n / a x x x x x x x x x x x x x x address mode format = 0 bit # dac output pin name data hex multiplier 0x10 0000 0x0100 0x0010 binar y position item
20 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com (continued next page) circuit description (continued) table 4. address map (8 channel format) channel functions (channels 0 to 3) channel 0 channel 2 channel 3 channel 1 note 1: all 6-bit dacs are programmed with the msb at the d12 bit position and extending down to d7 for the lsb. d[6:0] bit positions are don t cares . 23 22 21 20 19-16 15-12 11 10 9 8 7 6 5 43210 0x01 0000 0x1000 8421 8 - 1 8 - 1 84 21 8 4 2 18421 register r2 r1 r0 d12 d11 - d8 d7 - d4 d3 d2 d1 d0 m1 m0 c1 c0 a 3 a 2 a 1 a 0 vouta_0 xxxx x x xx xx000 00000 vouta_2 xxxx x x xx xx000 00010 reserved n / a xxxx x x xx xx000 00100 n/a group b 13-bit v voutb_0 xxxx x x xx xx000 00110 -3.5v to +13.75v ( 16.75v max swin g) group c 13-bit v/i voutc_0, ioutc_0 xxxx x x xx xx000 01000 v: -3.5v to +13.75v (16.75v max swing) i : 0.5ma to 2.05ma group d 6-bit i (note 1) ioutd_0 xxxx x x xx xx000 01010 0.8ma to 1.6ma pincast register 0 n / a xxxx x x xx xx000 01100 n/a select rank 1 calibration registers 000x x x xxx0 0 0 0 01110 select rank 2 calibration registers 000x x x xxx1 0 0 0 01110 configure group c dac as vout 000x x x xx0x 0 0 0 01110 configure group c dac as iout 000x x x xx1x 0 0 0 01110 vouta_1 xxxx x x xx xx000 00001 vouta_3 xxxx x x xx xx000 00011 reserved n / a xxxx x x xx xx000 00100 n/a group b 13-bit v voutb_1 xxxx x x xx xx000 00111 -3.5v to +13.75v ( 16.75v max swin g) group c 13-bit v/i voutc_1, ioutc_1 xxxx x x xx xx000 01001 v: -3.5v to +13.75v (16.75v max swing) i : 0.5ma to 2.05ma group d 6-bit i (note 1) ioutd_1 xxxx x x xx xx000 01011 0.8ma to 1.6ma pincast register 0 n / a xxxx x x xx xx000 01101 n/a select rank 1 calibration registers 000x x x xxx0 0 0 0 01111 select rank 2 calibration registers 000x x x xxx1 0 0 0 01111 configure group c dac as vout 000x x x xx0x 0 0 0 01111 configure group c dac as iout 000x x x xx1x 0 0 0 01111 vouta_4 xxxx x x xx xx000 10000 vouta_6 xxxx x x xx xx000 10010 reserved n / a xxxx x x xx xx000 10100 n/a group b 13-bit v voutb_2 xxxx x x xx xx000 10110 -3.5v to +13.75v ( 16.75v max swin g) group c 13-bit v/i voutc_2, ioutc_2 xxxx x x xx xx000 11000 v: -3.5v to +13.75v (16.75v max swing) i : 0.5ma to 2.05ma group d 6-bit i (note 1) ioutd_02 xxxx x x xx xx000 11010 0.8ma to 1.6ma pincast register 0 n / a xxxx x x xx xx000 11100 n/a select rank 1 calibration registers 000x x x xxx0 0 0 0 11110 select rank 2 calibration registers 000x x x xxx1 0 0 0 11110 configure group c dac as vout 000x x x xx0x 0 0 0 11110 configure group c dac as iout 000x x x xx1x 0 0 0 11110 vouta_5 xxxx x x xx xx000 10001 vouta_7 xxxx x x xx xx000 10011 reserved n / a xxxx x x xx xx000 10100 n/a group b 13-bit v voutb_3 xxxx x x xx xx000 10111 -3.5v to +13.75v ( 16.75v max swin g) group c 13-bit v/i voutc_3, ioutc_3 xxxx x x xx xx000 11001 v: -3.5v to +13.75v (16.75v max swing) i : 0.5ma to 2.05ma group d 6-bit i (note 1) ioutd_3 xxxx x x xx xx000 11011 0.8ma to 1.6ma pincast register 0 n / a xxxx x x xx xx000 11101 n/a select rank 1 calibration registers 000x x x xxx0 0 0 0 11111 select rank 2 calibration registers 000x x x xxx1 0 0 0 11111 configure group c dac as vout 000x x x xx0x 0 0 0 11111 configure group c dac as iout 000x x x xx1x 0 0 0 11111 -3.5v to +13.75v (16.75v max swin g ) n/a group a 13-bit v n/a n/a group a 13-bit v n/a group a 13-bit v group a 13-bit v dac output pin name data format = 1 bit # hex multiplier 0x10 0000 0x0100 binar y position item
21 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com table 4. address map (8 channel format) ?cont? (continued next page) circuit description (continued) channel functions (channels 4 to 7) channel 4 channel 5 channel 6 channel 7 note 1: all 6-bit dacs are programmed with the msb at the d12 bit position and extending down to d7 for the lsb. d[6:0] bit positions are don t cares . 23 22 21 20 19-16 15-12 11 10 9 8 7 6 5 4 3 2 1 0 0x01 0000 0x1000 8421 8 - 1 8 - 1 8 4 2 1 8 4 2 1 8 421 register r2 r1 r0 d12 d11 - d8 d7 - d4 d3 d2 d1 d0 m1 m0 c1 c0 a 3 a 2 a 1 a 0 vouta_8 x x x x x x x x x x 0 0 1 0 0 0 0 0 vouta_10 x x x x x x x x x x 0 0 1 0 0 0 1 0 reserved n / a x x x x x x x x x x 0 0 1 0 0 1 0 0 n / a group b 13-bit v voutb_4 x x x x x x x x x x 0 0 1 0 0 1 1 0 -3.5 to +13.75v ( 16.75v max swin g) group c 13-bit v/i voutc_4, ioutc_4 x x x x x x x x x x 0 0 1 0 1 0 0 0 v: -3.5 to +13.75v (16.75v max swing) i : 0.5ma to 2.05ma group d 6-bit i (note 1) ioutd_4 x x x x x x x x x x 0 0 1 0 1 0 1 0 0.8ma to 1.6ma pincast register 0 n / a x x x x x x x x x x 0 0 1 0 1 1 0 0 n / a select rank 1 calibration registers 0 0 0 x x x x x x 0 0 0 1 0 1 1 1 0 select rank 2 calibration registers 0 0 0 x x x x x x 1 0 0 1 0 1 1 1 0 configure group c dac as vout 0 0 0 x x x x x 0 x 0 0 1 0 1 1 1 0 configure group c dac as iout 0 0 0 x x x x x 1 x 0 0 1 0 1 1 1 0 vouta_9 x x x x x x x x x x 0 0 1 0 0 0 0 1 vouta_11 x x x x x x x x x x 0 0 1 0 0 0 1 1 reserved n / a x x x x x x x x x x 0 0 1 0 0 1 0 0 n / a group b 13-bit v voutb_5 x x x x x x x x x x 0 0 1 0 0 1 1 1 -3.5 to +13.75v ( 16.75v max swin g) group c 13-bit v/i voutc_5, ioutc_5 x x x x x x x x x x 0 0 1 0 1 0 0 1 v: -3.5 to +13.75v (16.75v max swing) i : 0.5ma to 2.05ma group d 6-bit i (note 1) ioutd_5 x x x x x x x x x x 0 0 1 0 1 0 1 1 0.8ma to 1.6ma pincast register 0 n / a x x x x x x x x x x 0 0 1 0 1 1 0 1 n / a select rank 1 calibration registers 0 0 0 x x x x x x 0 0 0 1 0 1 1 1 1 select rank 2 calibration registers 0 0 0 x x x x x x 1 0 0 1 0 1 1 1 1 configure group c dac as vout 0 0 0 x x x x x 0 x 0 0 1 0 1 1 1 1 configure group c dac as iout 0 0 0 x x x x x 1 x 0 0 1 0 1 1 1 1 vouta_12 x x x x x x x x x x 0 0 1 1 0 0 0 0 vouta_14 x x x x x x x x x x 0 0 1 1 0 0 1 0 reserved n / a x x x x x x x x x x 0 0 1 1 0 1 0 0 n / a group b 13-bit v voutb_6 x x x x x x x x x x 0 0 1 1 0 1 1 0 -3.5 to +13.75v ( 16.75v max swin g) group c 13-bit v/i voutc_6, ioutc_6 x x x x x x x x x x 0 0 1 1 1 0 0 0 v: -3.5 to +13.75v (16.75v max swing) i : 0.5ma to 2.05ma group d 6-bit i (note 1) ioutd_6 x x x x x x x x x x 0 0 1 1 1 0 1 0 0.8ma to 1.6ma pincast register 0 n / a x x x x x x x x x x 0 0 1 1 1 1 0 0 n / a select rank 1 calibration registers 0 0 0 x x x x x x 0 0 0 1 1 1 1 1 0 select rank 2 calibration registers 0 0 0 x x x x x x 1 0 0 1 1 1 1 1 0 configure group c dac as vout 0 0 0 x x x x x 0 x 0 0 1 1 1 1 1 0 configure group c dac as iout 0 0 0 x x x x x 1 x 0 0 1 1 1 1 1 0 vouta_13 x x x x x x x x x x 0 0 1 1 0 0 0 1 vouta_15 x x x x x x x x x x 0 0 1 1 0 0 1 1 reserved n/a x x x x x x x x x x 0 0 1 1 0 1 0 0 n/a group b 13-bit v voutb_7 x x x x x x x x x x 0 0 1 1 0 1 1 1 -3.5 to +13.75v ( 16.75v max swin g) group c 13-bit v/i voutc_7, ioutc_7 x x x x x x x x x x 0 0 1 1 1 0 0 1 v: -3.5 to +13.75v (16.75v max swing) i : 0.5ma to 2.05ma group d 6-bit i (note 1) ioutd_7 x x x x x x x x x x 0 0 1 1 1 0 1 1 0.8ma to 1.6ma pincast register 0 n / a x x x x x x x x x x 0 0 1 1 1 1 0 1 n / a select rank 1 calibration registers 0 0 0 x x x x x x 0 0 0 1 1 1 1 1 1 select rank 2 calibration registers 0 0 0 x x x x x x 1 0 0 1 1 1 1 1 1 configure group c dac as vout 0 0 0 x x x x x 0 x 0 0 1 1 1 1 1 1 configure group c dac as iout 0 0 0 x x x x x 1 x 0 0 1 1 1 1 1 1 -3.5 to +13.75v (16.75v max swin g ) n/a group a 13-bit v n/a n/a group a 13-bit v n/a group a 13-bit v group a 13-bit v dac output pin name data format = 1 bit # hex multiplier 0x10 0000 0x0100 binar y position item
22 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com 23 22 21 20 19-16 15-12 11 10 9 8 76543210 0x01 0000 0x1000 8421 8 - 1 8 - 1 842184218421 register r2 r1 r0 d12 d11 - d8 d7 - d4 d3 d2 d1 d0 m1 m0 c1 c0 a 3 a 2 a 1 a 0 all dacs parallel load of all dacs all dac output pins xxxx x x xxxx1000000x parallel load of denoted vouta dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). vouta_0 vouta_1 vouta_4 vouta_5 vouta_8 vouta_9 vouta_12 vouta_13 x x x x x x x x x x ps0 1 ps2 ps1 0 0 0 x parallel load of denoted vouta dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). vouta_2 vouta_3 vouta_6 vouta_7 vouta_10 vouta_11 vouta_14 vouta_15 x x x x x x x x x x ps0 1 ps2 ps1 0 0 1 x parallel load of denoted voutb dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb) across multiple e6435 devices. voutb_0 voutb_1 voutb_2 voutb_3 voutb_4 voutb_5 voutb_6 voutb_7 x x x x x x x x x x ps0 1 ps2 ps1 0 1 1 x parallel load of denoted voutc or ioutc dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). voutc_0 voutc_1 voutc_2 voutc_3 voutc_4 voutc_5 voutc_6 voutc_7 or ioutc_0 ioutc_1 ioutc_2 ioutc_3 ioutc_4 ioutc_5 ioutc_6 ioutc_7 x x x x x x x x x x ps0 1 ps2 ps1 1 0 0 x parallel load of denoted ioutd dacs assigned to the pincast "set" addressed using the ps2, ps1, ps0 bits (ps0 is lsb). ioutd_0 ioutd_1 ioutd_2 ioutd_3 ioutd_4 ioutd_5 ioutd_6 ioutd_7 x x x x x x x x x x ps0 1 ps2 ps1 1 0 1 x 0x0100 binar y position hex multiplier 0x10 0000 format = 1 bit # item dac output pin name data circuit description (continued) table 4. address map (8 channel format) ?cont? pincast set functions group a dacs group b dacs group c dacs group d dacs
23 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com circuit description (continued) dac value readback via dac_out voltage outputs each voltage output of the edge6435/6436 has high impedance fet(s) connected from the outputs to a common analog line, dac_out, that provides readback of each dac s value. the primary purpose of this feature is to provide means for diagnostics of correct dac functionality in an application that can monitor dac_out, and is not intended for dac calibration. the feature utilizes the normal address decoding, as shown in tables 3 and 4, as well as a "high" level on the test_mode pin (see truth table below). note: a clk input is not required to change the state of the dac_out pin when test_mode is toggled. to test an output, a dac should be loaded as described above. at this point, the dac_out pin, which is an analog output, will reflect the voltage at the addressed dac's output pin. note that dac_out is switched off when the parallel load is selected (address 64). this prevents a parallel connection of all the dac outputs when the scan feature is used. address decoder test_mode dac_out vout_ch0_1 vout_ch0_2 vout_ch0_3 figure 12. dac voltage output via dac_out e d o m _ t s e tt u o _ c a d 0f f o 1n o digital inputs all digital inputs are lv_ttl compatible inputs. digital outputs sdout and ldout are cmos outputs that switch between dgnd and dvdd. power supply sequence power supplies must be controlled such that they maintain correct polarity with respect to each other and ground at all times during power-up and power-down. the following sequence is recommended: 1. avee 2. avcc 3. avdd, vref 4. dvdd
24 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com current outputs the test_mode and dac_out pins on the edge6435/ 6436 are used in the same way as for voltage outputs. the scan circuits for current outputs are shown in figure 13. the voltage measured at the dac_out pin, using the configuration in figure 13, for group c and d current outputs are as follows: v dac_out_c = (r sense_c + r pad ) * i out_c where: r sense_c = 160 ? 30% r pad = 30 ? 30% and v dac_out_d = (r sense_d + r pad ) * i out_d where: r sense_d = 160 ? 30% r pad = 30 ? 30% the typical "on" resistance of the fet switch is 2 k ? , but can vary from 900 ? to 3 k ? as a function of process and output voltage. notes when using dac_out feature with multiple chips when multiple 6435/6436s are used on a board, and it is desired to gang the dac_out pins of these 6435/6436s, or gang the test_mode inputs to one point, it is required to protect the 6435/6436s against damage that the following rules be followed: 1) if test_mode inputs are ganged together, dac_out cannot be ganged, or invalid results will be observed at the dac_out pin and damage could occur to the device. hence, each dac_out pin on a 6435/6436 will have to be measured separately. 2) if dac_out is ganged, the test_mode is used to select only one dac at a time. figure 13. dac current output vs dac_out address decoder + iout_ch0_0 test_mode dac_out idac + iout_ch0_1 idac + iout_ch0_2 idac connect to virtual ground connect to virtual ground note: when address 64 is invoked (parallel load), scan is disabled. connect to virtual ground r sense r sense r pa d r pa d r pa d r sense circuit description (continued)
25 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com circuit description (continued) latched data readback via ld_out figure 14 provides a functional block diagram of the means to readback, via ld_out, the status of latch s input into a selected dac. a dac s latches are addressed for readback in the same way they are addressed to be written via the serial input, sdin. testmode rank dacsel shiftout* ld_out d r d a b sel 13 1 dac readback register c c 13 r r d a dacs rank a or rank b latches are selcted by the rank input for subsequent readback. readback is enabled internally by testmode high whereupon the selected dac s rank a or rank b latch outputs are loaded into the readback register by a leading edge of clkin while shiftout* is high. with shiftout* low, subsequent clocks into clkin will shift out, via ld_out, the status of the selected dac s latches of rank a or rank b. figure 14. latched data readback functional block diagram
26 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com application information figure 15. required external components vout vout iout iout dac voltage outputs vref dvdd dgnd agnd avee edge6435 avcc avdd +10.0v sgnd 0v +5v 5v 0v 0v +3.3v 2.5v agnd . . . . . . dac current outputs . . . . . . i ref r_master r_vgain_a i ref r_offset_a i ref r_vgain_b i ref r_offset_b r_offset_c i ref i ref r_vgain_c r_ i gain_c i ref i ref r_ i gain_d i ref for group a dacs gain and offset control for group b dacs gain and offset control for group c dacs gain and offset control (voltage) gnd the selection of r_master establishes i ref gnd connect to the same ground as agnd pins o r may be connected to dut gnd (via switchable buffer) on a per group basis. typical supplies rank dacen reset* note: pull-down resistors required on rank, dacen, and reset* to ensure they are low upon power-up. such resistors may be common to multiple edge6435s. note: power supply inputs avcc, avdd, dvdd and avee need bypass capacitors located at the in p uts to the chi p of 10 10 k ? 10 k ? 10 k ?
27 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com application information (continued) the e6435/e6436 can be configured to provide all of the dac levels required for 4 fully-featured high-speed pin channels or 8 fully-featured low-speed pin channels when used with other semtech pin electronics components. since each e6435/e6436 dac channel includes 2 sets of calibration registers, dac channels can be shared across two distinct functions in an application to minimize the overall number of level dacs required in a system. tables 5 and 6 show the recommended shorting scheme for a couple of possible pin electronics solutions. high-speed pin electronics solution: 1 e6435/e6436 per 4 channels 2 e7725 dual channel, high speed pin driver + comparator + load + signal clamp devices per 4 channels 2 e42x7 dual-channel, parametric measure- ment unit + clamps per 4 channels e7725 e7725 e42x7 e42x7 e6435/ e6436 channel 0 channel 1 channel 2 channel 3 6 3 4 6 / 5 3 4 6 e5 2 7 7 e7 x 2 4 e p u o r gi / vn o i t c n u fl o b m y sn o i t c n u fl o b m y s av l e v e l " h g i h " r e v i r dh v dd e s u t o na / n av l e v e l w o l " r e v i r dl v dd e s u t o na / n av p m a l c e g a t l o v r e p p uh c vp m a l c e g a t l o v r e p p uv l h av p m a l c e g a t l o v r e w o ll c vp m a l c e g a t l o v r e w o lv l l bv d l o h s e r h t r o t a r a p m o cc v c , a v cd l o h s e r h t r o t a r a p m o c r e w o ln i m v i bv d l o h s e r h t r o t a r a p m o cb v cd l o h s e r h t r o t a r a p m o c r e p p ux a m v i cv e g a t l o v n o i t a n i m r e tm c v , t v dd e s u t o na / n cv d e s u t o na / ng n i m m a r g o r p t n e r r u c / e g a t l o vp n i v ci t n e r r u c e c r u o s d a o lc s id e s u t o na / n ci t n e r r u c k n i s d a o lk s id e s u t o na / n di t s u j d a e t a r w e l s " + " r e v i r dj d a rd e s u t o na / n di t s u j d a e t a r w e l s " " r e v i r dj d a fd e s u t o na / n table 5. e6435/e6436 per-channel dac connectivity for high-speed pin driver, comparator, clamp and load solution featuring differential capability and fast settling pmu per pin
28 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com application information (continued) low-speed pin electronics solution: 1 e6435/e6436 per 8 channels 2 e7804 quad channel, driver + comparator + ctc per 8 channels devices per 4 channels 4 e42x7 dual-channel, parametric measure- ment unit + clamps per 8 channels 6 3 4 6 / 5 3 4 6 e4 0 8 7 e7 x 2 4 e p u o r gi / vt i u c r i c t c e n n o c r e t n in o i t c n u fl o b m y sn o i t c n u fl o b m y s av d e r i u q e r e n o nl e v e l " h g i h " r e v i r dh v dg n i m m a r g o r p t n e r r u c / e g a t l o vp n i v av d e r i u q e r e n o nl e v e l " w o l " r e v i r dl v dd l o h s e r h t r o t a r a p m o cn i m v i bv d e r i u q e r e n o nd l o h s e r h t r o t a r a p m o ca v cd l o h s e r h t r o t a r a p m o cx a m v i cv d e r i u q e r e n o nd l o h s e r h t r o t a r a p m o cb v cp m a l c e g a t l o v r e p p uv l h * ) 0 ( di r e t r e v n o c v o t it i u c r i c t s e t y t i u n i t n o cv i f c t cp m a l c e g a t l o v r e w o lv l l * ) 1 ( di r e t r e v n o c v o t ie g a t l o v t s e t y t i u n i t n o cv l c t cd e s u t o na / n * ) 2 ( di r e t r e v n o c v o t ie g a t l o v p u - l l u pp v pd e s u t o na / n * ) 7 - 3 ( di d e r i u q e r e n o nd e s u t o na / nd e s u t o na / n table 6. e6435/e6436 per-channel dac connectivity for low-speed pin driver, comparator, continuity test circuit, and per-pin pmu solution e7804 e42x7 e42x7 e6435/ e6436 channel 0 channel 1 channel 2 channel 3 e7804 e42x7 e42x7 channel 4 channel 5 channel 6 channel 7 *d(0), d(1), d(n) correspond to dac channels that are used for common continuity test voltage/current program- ming values across multiple e7804 devices and are shared with the lower voltage clamp threshold on the e42x7.
29 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com package information pin descriptions figure 16. 14 x 20 x 2.0 mm, 100-pin mqfp (with internal heat spreader, requires heat sink) ? ? ? n 1 e 1 d 1 d e 10 typ. a 2 a 1 ? 10 typ. ? a e a l a 1 b .17 max .25 c lead coplanarity seating plane standoff ddd m c a b s d s ccc c .30 rad. typ. .20 rad. typ. 1 notes: 1. all dimensions in millimeters (mm). 2. dimensions shown are nominal with tolerances indicated. 3. foot length l is measured at gage plane 0.25mm above the seating plane. 4. use ms-022 variation ga-1 for body dimensions. 5. use mo-112 variation ca-1 for body dimensions. 6. use variation ga-1 for lead form options and bb for body dime. 7. use variation gb-1 for lead form options and bb for body dime. 8. use variation gc-1 for lead form options and bb for body dime. 9. use ms-022 variation bb for body dimensions. 10. n.j.r. means no single jedec reference putline or standard. m m 0 . 2 , t n i r p t o o f m m 2 . 3 + y d o b k c i h t . s m i d. s l o t a. x a m5 3 . 2 1 a. x a m5 2 . 2 a0 1 . 0 0 . 2 d0 2 . 0 2 . 3 2 d 1 0 1 . 0 0 . 0 2 e0 2 . 0 2 . 7 1 e 1 0 1 . 0 0 . 4 1 l5 1 . 0 8 8 . ec i s a b5 6 . b8 3 . 0 ~ 4 2 . 0 ? 7 ? 0 1 ? 4 . ? 6 d d d. m o n2 1 . c c cx a m0 1 . . g w d . f e r c e d e j r o t a n g i s e d n o i t a i r a v8 e t o n
30 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com recommended operating conditions note: all supplies are referenced to agnd unless otherwise noted. r e t e m a r a pl o b m y sn i mp y tx a ms t i n u y l p p u s r e w o p g o l a n a e v i t i s o pc c v a0 . 8 +0 . 0 1 +0 . 5 1 +v 2 y l p p u s r e w o p g o l a n a e v i t i s o pd d v a5 7 . 4 +0 . 5 +5 2 . 5 +v 1 y l p p u s r e w o p e v i t a g e ne e v a5 2 . 5 0 . 5 5 7 . 4 v e g a t l o v e c n e r e f e rf e r v9 9 4 . 21 0 5 . 2v 1 y l p p u s g o l a n a l a t o tc c v a e e v a5 7 . 2 15 2 . 0 2v y l p p u s r e w o p l a t i g i dd n g d d d v d0 . 35 2 . 5 +v d n u o r g l a t i g i dd n g d5 . 0 05 . 0 +v e g a k c a p f o e c n a t s i s e r l a m r e h t e s a c o t n o i t c n u j t n e i b m a o t n o i t c n u j r i a l l i t s m p f l 0 0 1 m p f l 0 0 4 c j a j 4 . 2 1 8 2 2 . 5 2 1 . 2 2 ? w / c w / c ? w / c ? w / c ? e r u t a r e p m e t e s a ct e s a c 5 25 6 c ?
31 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com absolute maximum ratings stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. exposure to absolute maximum conditions for extended periods may affect device reliability. note: all supplies are referenced to agnd unless otherwise noted. r e t e m a r a pl o b m y sn i mx a ms t i n u y l p p u s g o l a n a e v i t i s o p 2 y l p p u s g o l a n a e v i t i s o p y l p p u s g o l a n a e v i t a g e n c c v a d d v a e e v a 5 . 0 5 . 5 6 1 + 5 . 5 + 5 . 0 + v v v y l p p u s r e w o p l a t i g i dd d v d5 . 0 5 . 5 +v y l p p u s r e w o p l a t o t e e v a c c v a d d v a c c v a d n g a d n g a d n g a f e r v 5 . 0 5 . 0 5 . 0 5 . 5 5 . 0 5 . 0 d n g a 5 . 1 2 + 0 . 6 1 + 5 . 5 + 5 . 0 + 5 . 0 + 5 . 0 + d d v a v v v v v v s e g a t l o v t u p n i l a t i g i d v 0 . 5 < d d v d v 0 . 5 > d d v d , e r o t s , d a o l , n i k l c , n i d s , k n a r , c i v l e s , e t a d p u * t e s e r 5 . 0 d n g d 5 . 0 d n g d 5 . 0 + d d v d 5 . 5 + v v s e g a t l o v t u p n i g o l a n av ] 4 : 1 [ f e r v , r e t s a m , v ] c : a [ _ t e s f f o ,v ] c : a [ _ n i a g 5 . 0 d n g a5 . 0 + d d v av s t n e r r u c t u p n i g o l a n a i ] d : c [ _ n i a g i r e t s a m 0 0 1 0 0 1 0 0 1 + 0 0 1 + a a s e g a t l o v t u p t u o g o l a n a c , b , a s p u o r g] c : a [ _ t u o v5 . 0 e e v a5 . 0 + c c v av s t n e r r u c t u p t u o g o l a n a t n e r r u c c d s u o u n i t n o c c , b , a s p u o r g] c : a [ _ t u o i0 0 3 0 0 3 +a e r u t a r e p m e t g n i t a r e p o t n e i b m a e r u t a r e p m e t e g a r o t s e r u t a r e p m e t n o i t c n u j e r u t a r e p m e t g n i r e d l o s ) n i p e h t m o r f " 5 2 . , s d n o c e s 5 ( a t s t j t l o s t 0 5 6 5 2 1 + 0 5 1 + 5 2 1 + 0 6 2 + c ? c ? c ? c ?
32 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com dc characteristics r e t e m a r a pl o b m y sn i mp y tx a ms t i n u s t u p n i l a t i g i d , e t a d p u , e r o t s , d a o l , n i k l c , n i d s ( , n e c a d , e d o m t s e t , * t e s e r , k n a r ) t a m r o f e g a t l o v w o l t u p n i e g a t l o v h g i h t u p n i v 0 . 3 d d v d v 3 . 3 < v 3 . 3d d v d v 5 2 . 5 t n e r r u c t u p n i l i v h i v h i i , l i i 0 . 2 6 . 2 1 8 . 0 1 v v v a s t u p t u o l a t i g i d ) t u o d l , t u o d s ( e g a t l o v w o l t u p t u o e g a t l o v h g i h t u p t u o w o l t n e r r u c t u p t u o h g i h t n e r r u c t u p t u o l o v h o v l o i h o i 4 . 2 4 . 0 4 . 0 d d v d 6 . 1 v v a m a m s t u p t u o e g a t l o v c a d ) s t u p t u o e g a t l o v ( c d n a , b , a s p u o r g n o i t u l o s e r 3 1s t i b e g n a r e g a t l o v t u p t u oe g n a r _ t u o v5 2 . 1 + e e v a5 2 . 1 c c v av n a p s e g a t l o v t u p t u on a p s _ t u o v0 . 85 7 . 6 1v e g n a r t e s f f o t u p t u ov t e s f f o 5 . 3 5 7 . 0 v e c n a i l p m o c t n e r r u c t u p t u oi e c n a i l p m o c 0 0 2 0 0 2 +a ) 7 1 e r u g i f ( r o r r e e g n a rr o r r e _ s f5 1 2 5 1 2 +v m ) 7 1 e r u g i f ( r o r r e t e s f f ov s o 5 3 5 3 +v m n o i t a r b i l a c t n i o p - 2 g n i w o l l o f r o r r e y t i r a e n i l l a r g e t n i ) 8 1 e r u g i f ( s t n i o p n o i t a r b i l a c % 0 8 - % 0 2 s c a d 6 3 4 6 e s c a d 5 3 4 6 e 4 8 4 + 8 + b s l b s l ) 9 1 e r u g i f ( s t n i o p n o i t a r b i l a c t n i o p d n e s c a d 6 3 4 6 e s c a d 5 3 4 6 e 4 8 4 + 8 + b s l b s l n o i t a r b i l a c t n i o p - 7 g n i w o l l o f r o r r e y t i r a e n i l l a r g e t n i , 0 6 4 5 , 5 9 0 4 , 0 3 7 2 , 5 6 3 1 , 0 : s t n i o p n o i t a r b i l a c ( ) 1 9 1 8 , 5 2 8 6 l n i2 2b s l ) 9 1 e r u g i f ( r o r r e y t i r a e n i l l a i t n e r e f f i dl n d1 1 +b s l o c p m e t n i a g 0 5 2c ? / v o c p m e t r o r r e t e s f f o 0 5 2c ? / v ) 0 = n e c a d ( e g a t l o v t u p t u o d e l b a s i d c a d 0 0 1 0 0 1 +v m ) k l a t s s o r c l e n n a h c - o t - l e n n a h c c d ( n o i t c a r e t n i c a d 1 1 +v m
33 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com dc characteristics (continued) r e t e m a r a pl o b m y sn i mp y tx a ms t i n u ) s t u p t u o t n e r r u c ( c p u o r g n o i t u l o s e r 3 1s t i b e g n a r t n e r r u c t u p t u ot u o i5 . 05 0 . 2a m e c n a i l p m o c e g a t l o v t u p t u o 2 . 0 0 . 3v ) 8 1 e r u g i f ( n o i t a r b i l a c g n i w o l l o f r o r r e y t i r a e n i l l a r g e t n i ) 8 1 e r u g i f ( s t n i o p n o i t a r b i l a c % 0 8 - % 0 2 ) 9 1 e r u g i f ( s t n i o p n o i t a r b i l a c t n i o p d n e l n i 7 7 7 + 7 + b s l b s l ) 9 1 e r u g i f ( r o r r e y t i r a e n i l l a i t n e r f f i dl n d1 1b s l ) 7 1 e r u g i f ( r o r r e e g n a r 0 7 0 7 +a ) 7 1 e r u g i f ( r o r r e t e s f f oi s o 0 2 0 2 +a o c p m e t n i a g 0 3 1 c ? / a p o c p m e t r o r r e t e s f f o 0 3c ? / a p t n e r r u c t u p t u o d e l b a s i d c a d 0 2 00 2 +a ) s t u p t u o t n e r r u c ( d p u o r g n o i t u l o s e r 6s t i b e g n a r t n e r r u c t u p t u ot u o i8 . 06 . 1a m e c n a i l p m o c e g a t l o v t u p t u o 2 . 0 0 . 3v ) 8 1 e r u g i f ( n o i t a r b i l a c g n i w o l l o f r o r r e y t i r a e n i l l a r g e t n i ) 8 1 e r u g i f ( s t n i o p n o i t a r b i l a c % 0 8 - % 0 2 ) 9 1 e r u g i f ( s t n i o p n o i t a r b i l a c t n i o p d n e l n i 5 7 0 . 0 5 7 0 . 0 5 7 0 . 0 + 5 7 0 . 0 + b s l b s l ) 0 2 e r u g i f ( r o r r e y t i r a e n i l l a i t n e r e f f i dl n d5 2 0 . 0 5 2 0 . 0 +b s l ) 7 1 e r u g i f ( r o r r e e g n a r 0 7 0 7 +a ) 7 1 e r u g i f ( r o r r e t e s f f oi s o 0 2 00 2a o c p m e t n i a g 0 5c ? / a p o c p m e t r o r r e t e s f f o 0 3c ? / a p t n e r r u c t u p t u o d e l b a s i d c a d 0 2 00 2 +a
34 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com dc characteristics (continued) figure 17. representation of dac offset error and range error for 13-bit dacs (6-bit dacs similar) figure 18. representation of 2-point dac integral non-linearity (inl) ideal real transfer characteristic is somewhere between "dotted" lines range error = deviation of real dac output from ideal dac output at max code offset error = deviation of real dac from ideal dac at min code min code max code minimum range maximum range dac code dac output (voltage or current) straight lin e through20 % and 80% points dac integral non-linearity (inl) measured dac output at 80% of max code measured dac output at 20% of max code min code max code minimum range maximum range dac code dac output (voltage or current) range error and offset error are due to e6435/6436 only. external resistor tolerances and vref tolerance not included.
35 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com dc characteristics (continued) figure 20. representation of differential non-linearity (dnl) dac output (lsb) dac code measured dac output must not change by more than dnl specification limits between adjacent dac codes across the entire dac range 14 13 12 11 10 9 8 7 6 5 4 3 2 1 n+14 n+13 n+12 n+11 n+10 n+9 n+8 n+7 n+6 n+5 n+4 n+3 n+2 n+1 n figure 19. representation of 2-point dac integral non-linearity (inl) straight lin e through end poi nts dac integral non-linearity (inl) measured dac output at max code measured dac output at min code min code max code minimum range maximum range dac code dac output (voltage or current)
36 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com r e t e m a r a pl o b m y sn i mp y tx a ms t i n u ) 1 e t o n ( n o i t p m u s n o c y l p p u s r e w o p ) c c v a ( y l p p u s g o l a n a e v i t i s o pc c i5 10 2a m ) d d v a ( y l p p u s g o l a n a e v i t i s o pd d a i0 20 3a m ) d d v d ( y l p p u s l a t i g i d v 0 . 3 d d v d v 3 . 3 < v 3 . 3d d v d v 5 2 . 5 d d d i 0 5 20 0 5 0 0 8 a a ) e e v a ( y l p p u s r e w o p e v i t a g e ne e i0 5 0 3 a m y l p p u s e c n e r e f e rf e r i2 . 0 2 . 0 +a dc characteristics (continued) power supplies note 1: clkin low, quiescent. r e t e m a r a pl o b m y sn i mp y tx a ms t i n u o i t a r n o i t c e j e r y l p p u s r e w o pr r s p t u p t u o c a d y n a o t c c v a c d z h k 0 0 1 z h k 0 0 5 z h m 1 8 8 7 2 0 2 8 1 b d b d b d b d t u p t u o c a d y n a o t e e v a c d z h k 0 0 1 z h k 0 0 5 z h m 1 6 6 8 5 3 1 b d b d b d b d t u p t u o c a d y n a o t d d v a c d z h k 0 0 1 z h k 0 0 5 z h m 1 2 6 3 8 1 6 2 b d b d b d b d
37 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com ac characteristics r e t e m a r a pl o b m y sn i mp y tx a ms t i n u s t u p n i l a t i g i d ) e g d e g n i s i r n i k l c o t ( s e m i t p u t e s n i d s d a o l e r o t s e t a d p u * t e s e r n e c a d * t u o t f i h s t i d s _ u s t d l _ u s r t s _ u s t d p u _ u s t t s r _ u s t n e d _ u s t t u o s _ u s t 2 2 2 2 2 2 2 s n s n s n s n s n s n s n s e m i t d l o h ) e g d e g n i s i r n i k l c o t ( n i d s d a o l e r o t s e t a d p u * t u o t f i h s t i d s _ d l h t d l _ d l h r t s _ d l h t d p u _ d l h t t u o s _ d l h t 2 2 2 2 2 s n s n s n s n s n ) e g d e g n i s i r n i k l c o t ( s e m i t t u p t u o t u o d s t u o d l t u o d s _ o t t u o d l _ o t 8 1 8 1 s n s n n i k l c x a m f v 3 . 3 o t v 0 . 3 = d d v d v 5 2 . 5 o t v 5 7 . 4 = d d v d f x a m 0 6 0 8 z h m z h m g n i c a p s k c o l c h t d i w k c o l c k c _ s c k c _ w c 5 5 s n s n h t d i w e s l u p t e s e rw p t e s e r 3s n ) 2 e t o n ( e m i t g n i l t t e s t u p t u o c a d ) 1 9 1 8 o t 0 e d o c c a d ( p e t s e l a c s - l l u f ) c , b , a s p u o r g ( s c a d e g a t l o v e g n a r v 6 1 r o r r e y t i r a e n i l d e i f i c e p s o t g n i l t t e s r s f % 5 . 0 o t g n i l t t e s e g n a r v 8 r o r r e y t i r a e n i l d e i f i c e p s o t g n i l t t e s r s f % 5 . 0 o t g n i l t t e s v e l t t e s 5 6 0 5 0 3 0 3 s s s s s c a d t n e r r u c c p u o r r g r o r r e y t i r a e n i l d e i f i c e p s o t g n i l t t e s r s f % 5 . 0 o t g n i l t t e s ) 3 6 o t 0 e d o c c a d , p e t s e l a c s - l l u f ( d p u o r r g r o r r e y t i r a e n i l d e i f i c e p s o t g n i l t t e s r s f % 5 . 0 o t g n i l t t e s 5 4 5 3 0 4 0 3 s s s s ) 1 e t o n ( e m i t k c a b d a e r t u o _ c a d 3 . 25s ) 4 e t o n ( e m i t e l b a n e t u p t u o c a d e g a t l o vv e o t 4s ) 5 e t o n ( e m i t e l b a s i d t u p t u o c a d e g a t l o vv z t 8 1s ) 4 e t o n ( e m i t e l b a n e t u p t u o c a d t n e r r u ci e o t 5 . 1s ) 6 e t o n ( e m i t e l b a s i d t u p t u o c a d t n e r r u ci z t 7s ) 3 e t o n ( e m i t n o i t i s n a r t k n a rt k n a r 5 . 1s
38 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com ac characteristics (continued) figure 22. shift register loading timing diagram figure 21. individual dac storing and dac updating (reset* high) ck24 clkin load tsu_ld thld_ld tsu_rnk thld_rnk tsu_rnk thld_rnk c 3c 16c 2c store tsu_str tsu_str thld_str tsu_upd thld_upd tsu_upd updatea (internal) update _ _ _ _ _ _ _ rank _ _ _ _ _ _ _ _ sdin ckin sdout ck1 ck24 valid data a0 previous a0 a1 valid data r2 t su_sdi t su_sdi t hld_sdi t hld_sdi to_sdout note 1: dac_out readback time is the amount of time required for dac_out to display a valid voltage for a selected (and fully settled) dac channel and only includes channel-to-channel switching time. note 2: measured from clkin using edge of update to specified accuracy. note 3: rank transition time is a measurement of the time required to change between rank a and rank b latches and does not include dac output settling time. note 4: dac output enable time is measured after dacen is transitioned from 0 to 1 from the rising edge of the clock signal applied to clkin as the time required for the dac output to change by 10%. note 5: voltage dac output disable time is measured from the falling edge of dacen as the amount of time required for the dac output to change from positive full-scale to 0.5v. note 6: current dac output disable time is measured from the falling edge of dacen as the amount of time required for the dac output to change by 10%.
39 test and measurement products ? 2006 semtech corp. / rev. 3, 8/25/06 edge6435/6436 www.semtech.com ac characteristics (continued) figure 23. reset* and dacen timing figure 24. shiftout*, ldout timing tsu_rst tsu_den clkin dacen reset* tsu_sout tsu_sout thld_sout to_ldout clkin load store or update rank, testmode shiftout* ldout d0 d1 1 c 1 c > 0 ns
40 ? 2006 semtech corp. / rev. 3, 8/25/06 test and measurement products edge6435/6436 www.semtech.com ordering information contact information semtech corporation test and measurement division 10021 willow creek rd., san diego, ca 92131 phone: (858)695-1808 fax (858)695-2633 r e b m u n l e d o me g a k c a p t f h b 5 3 4 6 e p f q m n i p 0 0 1 , m m 2 x 0 2 x 4 1 ) r e d a e r p s t a e h l a n r e t n i h t i w ( 5 3 4 6 m v ed r a o b n o i t a u l a v e 5 3 4 6 e g d e t f h b 6 3 4 6 e p f q m n i p 0 0 1 , m m 2 x 0 2 x 4 1 ) r e d a e r p s t a e h l a n r e t n i h t i w ( 6 3 4 6 m v ed r a o b n o i t a u l a v e 6 3 4 6 e g d e pb this product is lead-free.

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